# High Level Design

Group:

{% include 'group.md' %}

## Hardware top level block diagram

Full FlexDI module block diagram:

![Hardware top level block diagram](res/SoC_FlexDI_Block_Diagram.svg)

State machine

![Hardware diagram of PIO block](res/SoC_FlexDI_SM_Block_Diagram.svg)

## Software top level block diagram

![Software Block diagram](./res/SoC_PIO_SW_block_Diagram2.svg)

## Module specification

This project aims to be fully compatible with the existing PIO Hardware.
For this reason the register specification is exactly the same as specified in
the [official documentation](https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#page=371&zoom=100,153,108).
This may be subject to change and could differ in the future.

### Verilog module: PIO

**Function:**
- Top level module of programmable IO block

**Interface:**
- student
  - TL-UL
  - GPIOs

**Verification plan:**
- Run the for examples mentioned in the Requirements & Functional Specification

### Verilog module: Instruction memory

**Function:**
- Holds the instructions necessary for FlexDI Cores
- implemented as 4-read 1-write memory block

**Interface:**
- flexdi
  - tlul_adapter
  - Instruction multiplexer

**Verfication plan:**
- Verilog testbench, self-testing

### Verilog module: Instruction multiplexer

**Function:**
- Multiplexes instructions from the instruction memory (TL-UL adapter), forced instructions (TL-UL adapter) and EXE instructions from the Core

**Interface:**
- flexdi
  - Instruction memory
  - Instruction decoder
  - Core

**Verfication plan:**
- Tested with PIO-C-Examples integrated into the whole system

### Verilog module: State machine

**Function:**
- Grouping module for the individual state machines running the instructions
- Pass through interfaces of sumbodules

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

#### Verilog module: Fractional divider

**Function:**
- Enable the state machine to run at a clock speed different from the main system
- Provide a clock to all state machine components

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

#### Verilog module: Instruction decoder

**Function:**
- Decode instructions from memory
- Set core operation flags

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

#### Verilog module: Core

**Function:**
- Apply instructions to FIFO, In/Out shift registers and scratch registers
- Advance program counter

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

#### Verilog module: Scratch registers

**Function:**
- Hold temporary values for the state machine's operations

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

#### Verilog module: Setup + Status registers

**Function:**
- Enable main CPU to configure the state machine's operation (speed, IRQs, force instruction, etc.)
- Allow debugging of state machine through exposing state machine status (program counter, etc.) in status registers

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Tested by integration with the other modules

### Verilog module: Output shift register (OSR)

**Function:**
- Facilitate serializing words from TX FIFO to bits for processing

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

### Verilog module: Input shift register (ISR)

**Function:**
- Facilitate deserializing bits into words for RX FIFO after processing

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

### Verilog module: FIFO

**Function:**
- Instanced as asynchronous Input/Output FIFO for all the state machines
- Two per state machine

**Interface:**
- No direct external interface
- Configuration using the DMA adapter

**Verfication plan:**
- Verilog testbench, self-testing

### Verilog module: DMA Adapter

**Function:**
- Configuration unit
- Allows for configuration
- of almost all other components in the system

**Interface:**
```{reggen} flexDI
```

**Verfication plan:**
- Verilog testbench, self-testing

### Verilog module: IRQ Adapter

**Function:**
- Manages internal State machine IRQs
- Manages external irq selection

**Interface:**
- IRQ line input from CPU
- configuration using DMA Adapter registers

**Verfication plan:**
- Verilog testbench, self-testing

### Verilog module: IO Mapper

**Function:**
- GPIO selection Matrix
- allows for selection and/or driving of multiple GPIO ports by state machines

**Interface:**
- connection to GPIO Pins

**Verfication plan:**
- Verilog testbench, self-testing