.. _ex1_submission:

Ex. 1: HDL entry and simulation
===============================

Group: **rvlab01**

Status register (0x0)
---------------------

+--------+-----------------+
| 31:8   | 7:0             |
+========+=================+
| unused | shifted pattern |
+--------+-----------------+
|        |       R         |
+--------+-----------------+

Mode register (0x4)
-------------------

+--------+------+
| 31:2   | 1:0  |
+========+======+
| unused | Mode |
+--------+------+
|        | R/W  |
+--------+------+

### Mode
- `0b00`: stop
- `0b01`: right-to-left
- `0b10`: left-to-right
- `0b11`: ping-pong

Speed register/Pause count register (0x8)
-----------------------------------------

+--------------------------------------------------+
| 31:0                                             |
+==================================================+
| counter in cycles until the next shift operation |
| R/W                                              |
+--------------------------------------------------+

Pattern register (0xC)
----------------------

+--------+---------------------------------+
| 31:8   | 7:0                             |
+========+=================================+
| unused | pattern that will be shifted    |
|        | R/W                             |
+--------+---------------------------------+


Usage
-----

All writable registers may be changed at any time.
On Mode register change the Pattern is being applied.
The speed register value will be applied immediately.

When the state is changed to `stop`, the system does not reset the pattern and
instead stays at the last shifted pattern. On the next state change, it will reset.

Source code
-----------
Appended in the following order

1. [Testbench](#testbench) (src/fv/student_rlight_tb.sv)
2. [rlight module](#rlight-module) (src/rtl/student/student_rlight.sv)