Resources

Xilinx Hardware & Design Tools

• 7 Series Product Tables and Product Selection Guide (XMP101) The last page contains links to the most important user guides (CLBs, rams, DSPs, IOs, …)

• Vivado Design Suite User Guide: Synthesis (UG901) HDL templates for inferring block rams (inferring as (simpler) alternative to instantiate library primitives). Only works for Vivado.

• Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide UG953 (v2021.2) October 22, 2021 Instance templates for all library primitives

• UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292)

• Vivado Design Suite Tcl Command Reference Guide (UG835)

• Vivado Design Suite Properties Reference Guide (UG912)

Digilent Nexys Video FPGA Board:

• Nexys Video Reference Manual (local PDF copy)

• Nexys Video schematic

RISC-V System

• RISC-V Reference card

• RISC-V Instruction Set Manual Vol. I: Unprivileged ISA

• RISC-V Instruction Set Manual Vol. II: Privileged ISA

• TileLink Spec (local PDF copy)

• OpenTitan’s Reggen manual (differs in details from the version used in rvlab!)

• OpenTitan’s Crossbar Generation tool manual (differs in details from the version used in rvlab!)

• Ibex Documentation

SystemVerilog

• System Verilog for synthesis

• Verilog Language reference manual (LRM) (the authoritative source to consult for in depth questions, e.g. how a certain language element is to be handeled by a simulator).

TUB

• Modulbeschreibung

• MSC Website

Recommended External IP

The following projects are not integrated into rvlab but could (i.e. no guarantee) be useful for student projects:

• verilog-ethernet

• HDMI output

  • basic explanation & (overly simplified - do not use) implementation: fpga4fun

  • DVI only, no sound: display_controller

  • HDMI, with sound: hdmi

• HDMI input

  • litevideo (part of LiteX project, python rendered verilog):