RISC-V Lab

Contents:

  • Exercise Sheets & Slides
  • Project
  • Design Reference
    • Core Overview
    • FPGA Board
    • Directory Structure
    • Memory Map
    • Generated Registers
    • Clocks and Resets
    • DDR3 Memory
    • Design Flow Reference
  • Tutorials
  • Resources
  • Submissions
  • FlexDI
RISC-V Lab
  • Design Reference
  • View page source

Design Reference

Contents:

  • Core Overview
    • Student module
  • FPGA Board
    • External Components
    • Mechanical Design
  • Directory Structure
  • Memory Map
  • Generated Registers
    • Register demo
    • DDR3 control
    • RISC-V timer
  • Clocks and Resets
    • Multi-FF Synchronizers
  • DDR3 Memory
  • Design Flow Reference
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