RISC-V Lab

Contents:

  • Exercise Sheets & Slides
  • Project
  • Design Reference
  • Tutorials
  • Resources
  • Submissions
    • Ex. 1: HDL entry and simulation
    • Ex. 2: Logic synthesis, P&R and netlist simulation
    • Ex. 3: Software development and system simulation
    • Ex. 4: DMA / TL-UL host implementation
    • Ex. 5: Hierarchical buses and cascaded interrupts
  • FlexDI
RISC-V Lab
  • Submissions
  • View page source

Submissions

Report of exercises:

  • Ex. 1: HDL entry and simulation
    • Status register (0x0)
    • Mode register (0x4)
    • Speed register/Pause count register (0x8)
    • Pattern register (0xC)
    • Usage
    • Source code
  • Ex. 2: Logic synthesis, P&R and netlist simulation
    • 1. Questions
    • 2. Deliverables of task 3
  • Ex. 3: Software development and system simulation
    • 1. Questions
    • 2. Deliverables of task 4
    • Appendix:
  • Ex. 4: DMA / TL-UL host implementation
    • 1. Source texts
    • 2. Wave views
    • memcpy_hard
    • memcpy_soft
    • Appendix:
  • Ex. 5: Hierarchical buses and cascaded interrupts
    • 1. Questions
    • 2. Source texts
    • 3. Wave Views
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