RISC-V Lab

Contents:

  • Exercise Sheets & Slides
    • Ex. 1: HDL entry and simulation
    • Ex. 2: Logic synthesis, P&R and netlist simulation
    • Ex. 3: Software development and system simulation
    • Ex. 4: DMA / TL-UL host implementation
    • Ex.5: Hierarchical buses and cascaded interrupts
    • Slides
  • Project
  • Design Reference
  • Tutorials
  • Resources
  • Submissions
  • FlexDI
RISC-V Lab
  • Exercise Sheets & Slides
  • View page source

Exercise Sheets & Slides

Exercises are now separated from the project part. The Project section explains tasks for the project part.

Sheets

  • Ex. 1: HDL entry and simulation
    • Objectives
    • Preparation
    • Tasks
  • Ex. 2: Logic synthesis, P&R and netlist simulation
    • Objectives
    • Preparation
    • Tasks
    • Deliverables
  • Ex. 3: Software development and system simulation
    • Objectives
    • Preparation
    • Tasks
    • Deliverables
  • Ex. 4: DMA / TL-UL host implementation
    • Objectives
    • Preparation
    • Tasks
    • Deliverables
  • Ex.5: Hierarchical buses and cascaded interrupts
    • Objectives
    • Preparation
    • Tasks
    • Deliverables

Slides

Exercise 1 Slides

Exercise 2 Slides

Exercise 3 Slides

Exercise 4 Slides

Exercise 5 Slides

Exercise 6 Slides

Exercise 7 Slides

Exercise 8 Slides

Exercise 9 Slides

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