Ex. 2: Logic synthesis, P&R and netlist simulation

Objectives

  • get an overview of the rvlab HDL design

  • logic synthesis and P&R

    • use synthesis log files to identify (and fix) non synthesizable HDL

    • interpret timing reports and locate reported paths in the design

  • netlist simulation

    • locate RTL elements in the netlist simulation

    • evaluate timing error messages

Preparation

  • Explore the rvlab HDL design: Traverse the design hierarchy of rvlab from the top level test bench system_tb through fpga core and through student to your student_rlight. At leach level make yourself familiar with the instances instantiated and their major connections.

  • Read the tutorial FPGA Implementation (Synthesis, Place and Route).

  • Use the Xilinx Documentation Navigator (see Resources page) to get an overview of the available Xilinx documentation.

Tasks

Hints

  • The following tasks 1-3 build upon each other. Only proceed to the next task when the previous has been completed successfully.

  • You can try out all tasks listed below with the original student_rlight supplied instead of your own running light. Especially this provides a reference for the synthesis and P&R warnings which can be ignored.

1. System simulation with software

Your design student_rlight is already instantiated in the rvlab SoC. So no changes to the HDL are required.

The software template for this exercise is located in rvlab/src/rlight/main.c. Modify it to read and write all registers of your module at least once and test all modes of the running light with different parameters (see Deliverables below).

The following command starts a simulation which uses the JTAG interface to upload your software into the design and executes it:

flow systb_rlight.sim_rtl_questa

2. Logic synthesis and place & route

2.1. Perform a logic synthesis of rvlab_fpta_top:

flow rvlab_fpga_top.syn

Examine all generated files in rvlab/build/rvlab_fpga_top/syn. Check the synthesis (vivado.log) and timing reports (rvlab_fpga_top.timing_summary.txt) for warning and error messages associated with your student_rlight.

2.2. Perform a place and route of rvlab_fpga_top:

flow rvlab_fpga_top.pnr

Examine all generated files in rvlab/build/rvlab_fpga_top/pnr. Check the place and route reports (vivado.log) for warning and error messages associated with your rvlab_student_rlight. Read the timing reports (rvlab_fpga_top.timing_summary.txt) and locate the reported paths in the RTL.

Examine the resulting schematic and layout with the tool “vivado”:

vivado build/rvlab_fpga_top/pnr/rvlab_fpga_top.dcp &

2.3. Generate the bitfile:

flow rvlab_fpga_top.bitstream

Examine all generated files in rvlab/build/rvlab_fpga_top/bitstream. Check the log file vivado.log for any warning and error messages. Check rvlab_fpga_top.io_report.txt for any unplaced IOs. Any issues might kill the FPGA, so these files need to be signed of by the tutor before any upload.

Refer to the FPGA Implementation (Synthesis, Place and Route) regarding details of the flow for synthesis and P&R.

3. FPGA netlist simulation

All previous simulations only tested the functionality as described in HDL. However, these simulations do not allow any judgment whatsoever about the synthesizability of the HDL sources or even the behavior of the resulting circuit. This can only be verified by simulating the netlist and the associated SDF file which are generated by the Place & Route tool from the implemented FPGA structure. This netlist simulation saves one from a hopeless, endless debugging session on the real board.

Run a netlist simulation using QuestaSim with the software developed in task 1 to generate the Deliverables:

flow systb_rlight.sim_pnrtime_questa

Deliverables

All deliverables should be submitted in a single PDF file.

1. Questions

  1. Which files contain the definition of the TL-UL and board level (DDR3, LED, …) connections ?

  2. What is the maximum operating speed in Megahertz of the main clk “clk” after the Place & Route ?

  3. Name the three most important differences between functional simulation of the HDL and netlist simulation.

2. Deliverables of task 3:

Wave views

The wave views should be zoomed in as much as possible to only show the sections specified below. At least the following signals should be shown of your running light: clk, LEDs, state, delay counter and register bus at tlul_adapter_reg).

  1. While the running light is running with a pause time of 5 cycles: A write access (writing 0x42) to the delay register followed by a read access.

  2. Two complete cycles with the following configurations: #. mode=right, initial pattern=11111110, pause = 1 cycle #. mode=ping-pong, initial pattern=10000000, pause = 0 cycles (i.e. the pattern changes every clock cycle)

  3. A read access to the pattern register which clearly shows the delayed arrival of the data at register bus after the rising clock edge.