High Level Design

Group:

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Hardware top level block diagram

Full FlexDI module block diagram:

State machine

Software top level block diagram

Module specification

This project aims to be fully compatible with the existing PIO Hardware. For this reason the register specification is exactly the same as specified in the official documentation. This may be subject to change and could differ in the future.

Verilog module: PIO

Function:

• Top level module of programmable IO block

Interface:

• student

  • TL-UL

  • GPIOs

Verification plan:

• Run the for examples mentioned in the Requirements & Functional Specification

Verilog module: Instruction memory

Function:

• Holds the instructions necessary for FlexDI Cores

• implemented as 4-read 1-write memory block

Interface:

• flexdi

  • tlul_adapter

  • Instruction multiplexer

Verfication plan:

• Verilog testbench, self-testing

Verilog module: Instruction multiplexer

Function:

• Multiplexes instructions from the instruction memory (TL-UL adapter), forced instructions (TL-UL adapter) and EXE instructions from the Core

Interface:

• flexdi

  • Instruction memory

  • Instruction decoder

  • Core

Verfication plan:

• Tested with PIO-C-Examples integrated into the whole system

Verilog module: State machine

Function:

• Grouping module for the individual state machines running the instructions

• Pass through interfaces of sumbodules

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: Fractional divider

Function:

• Enable the state machine to run at a clock speed different from the main system

• Provide a clock to all state machine components

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: Instruction decoder

Function:

• Decode instructions from memory

• Set core operation flags

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: Core

Function:

• Apply instructions to FIFO, In/Out shift registers and scratch registers

• Advance program counter

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: Scratch registers

Function:

• Hold temporary values for the state machine’s operations

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: Setup + Status registers

Function:

• Enable main CPU to configure the state machine’s operation (speed, IRQs, force instruction, etc.)

• Allow debugging of state machine through exposing state machine status (program counter, etc.) in status registers

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Tested by integration with the other modules

Verilog module: Output shift register (OSR)

Function:

• Facilitate serializing words from TX FIFO to bits for processing

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: Input shift register (ISR)

Function:

• Facilitate deserializing bits into words for RX FIFO after processing

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: FIFO

Function:

• Instanced as asynchronous Input/Output FIFO for all the state machines

• Two per state machine

Interface:

• No direct external interface

• Configuration using the DMA adapter

Verfication plan:

• Verilog testbench, self-testing

Verilog module: DMA Adapter

Function:

• Configuration unit

• Allows for configuration

• of almost all other components in the system

Interface:

flexDI.CTRL @ + 0x0 FlexDI control register Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   CLKDIV_RESTART SM_RESTART SM_ENABLE
Bits	Type	Reset	Name	Description
3:0	rw	0x0	SM_ENABLE	Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously
7:4	rw	0x0	SM_RESTART	Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The program counter, the contents of the output shift register and the X/Y scratch registers are not affected
11:8	rw	0x0	CLKDIV_RESTART	Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in" precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."

flexDI.FSTAT @ + 0x4 FIFO status register Reset default = 0xf000f00, mask 0xf0f0f0f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   TXEMPTY   TXFULL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   RXEMPTY   RXFULL
Bits	Type	Reset	Name	Description
3:0	ro	0x0	RXFULL	RX Fifo of state machine is full
7:4				Reserved
11:8	ro	0xf	RXEMPTY	RX Fifo of state machine is empty
15:12				Reserved
19:16	ro	0x0	TXFULL	RX Fifo of state machine is full
23:20				Reserved
27:24	ro	0xf	TXEMPTY	TX Fifo of state machine is empty

flexDI.FDEBUG @ + 0x8 FIFO Debug Register Reset default = 0x0, mask 0xf0f0f0f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   TXSTALL   TXOVER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   RXUNDER   RXSTALL
Bits	Type	Reset	Name	Description
3:0	rw	0x0	RXSTALL	state machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.
7:4				Reserved
11:8	rw	0x0	RXUNDER	RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.
15:12				Reserved
19:16	rw	0x0	TXOVER	TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped" some data on the floor."
23:20				Reserved
27:24	rw	0x0	TXSTALL	state machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear

flexDI.FLEVEL @ + 0xc Current Fill levels of all FIFOs Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RX3 TX3 RX2 TX2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX1 TX1 RX0 TX0
Bits	Type	Reset	Name	Description
3:0	ro	0x0	TX0	Fill Level of TX Fifo of state Machine 0
7:4	ro	0x0	RX0	Fill Level of RX Fifo of state Machine 0
11:8	ro	0x0	TX1	Fill Level of TX Fifo of state Machine 1
15:12	ro	0x0	RX1	Fill Level of RX Fifo of state Machine 1
19:16	ro	0x0	TX2	Fill Level of TX Fifo of state Machine 2
23:20	ro	0x0	RX2	Fill Level of RX Fifo of state Machine 2
27:24	ro	0x0	TX3	Fill Level of TX Fifo of state Machine 3
31:28	ro	0x0	RX3	Fill Level of RX Fifo of state Machine 3

flexDI.TXF0 @ + 0x10 Direct Write Access to TX Fifo Reset default = 0x0, mask 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	wo	x	Data	Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

flexDI.TXF1 @ + 0x14 Direct Write Access to TX Fifo Reset default = 0x0, mask 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	wo	x	Data	Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

flexDI.TXF2 @ + 0x18 Direct Write Access to TX Fifo Reset default = 0x0, mask 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	wo	x	Data	Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."

flexDI.TXF3 @ + 0x1c Direct Write Access to TX Fifo Reset default = 0x0, mask 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	wo	x	Data	Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

flexDI.RXF0 @ + 0x20 Direct Read Access from RX Fifo Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	ro	0x0	Data	Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

flexDI.RXF1 @ + 0x24 Direct Read Access from RX Fifo Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	ro	0x0	Data	Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

flexDI.RXF2 @ + 0x28 Direct Read Access from RX Fifo Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	ro	0x0	Data	Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

flexDI.RXF3 @ + 0x2c Direct Read Access from RX Fifo Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Data
Bits	Type	Reset	Name	Description
31:0	ro	0x0	Data	Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

flexDI.IRQ Register @ + 0x30 IRQ Flags of state Machines Reset default = 0x0, mask 0xff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   IRQ Flags
Bits	Type	Reset	Name	Description
7:0	rw	0x0	IRQ Flags	state machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines — any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts — see e.g. IRQ0_INTE.

flexDI.IRQ FORCE @ + 0x34 Register to Force IRQs for Software tests Reset default = 0x0, mask 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   IRQ Fields
Bits	Type	Reset	Name	Description
7:0	wo	x	IRQ Fields	Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects FlexDI internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.

flexDI.INPUT_SYNC_BYPASS @ + 0x38 Bypass 2FF Synchronizer of GPIOs Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Input Sync Bypass... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...Input Sync Bypass
Bits	Type	Reset	Name	Description
31:0	rw	0x0	Input Sync Bypass	There is a 2-flipflop synchronizer on each GPIO input, which protects FlexDI logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 → input is synchronized (default) 1 → synchronizer is bypassed If in doubt, leave this register as all zeroes.

flexDI.DBG_PADOUT @ + 0x3c GPIO Pad Output Debug Register Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO Output Values... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...GPIO Output Values
Bits	Type	Reset	Name	Description
31:0	ro	0x0	GPIO Output Values	Read to sample the pad output values FlexDI is currently driving to the GPIOs. There can be up to 32 GPIOs per FlexDI Unit

flexDI.DBG_PADOE @ + 0x40 GPIO Pad Output Enable Debug Register Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO Output Enables... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...GPIO Output Enables
Bits	Type	Reset	Name	Description
31:0	ro	0x0	GPIO Output Enables	Read to sample the pad output enables (direction) FlexDI is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

flexDI.DBG_CFGINFO @ + 0x44 Configuration Debug Register Reset default = 0x0, mask 0x3f0f3f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   IMEM_SIZE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM_COUNT   FIFO_DEPTH
Bits	Type	Reset	Name	Description
5:0	ro	0x0	FIFO_DEPTH	The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth.
7:6				Reserved
11:8	ro	0x0	SM_COUNT	Number of state machines of this FlexDI instance
15:12				Reserved
21:16	ro	0x0	IMEM_SIZE	The Size of the instruction memory, measured in units of one instruction

flexDI.INSTR_MEM0 @ + 0x48 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM1 @ + 0x4c Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM2 @ + 0x50 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM3 @ + 0x54 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM4 @ + 0x58 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM5 @ + 0x5c Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM6 @ + 0x60 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM7 @ + 0x64 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM8 @ + 0x68 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM9 @ + 0x6c Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM10 @ + 0x70 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM11 @ + 0x74 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM12 @ + 0x78 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM13 @ + 0x7c Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM14 @ + 0x80 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM15 @ + 0x84 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM16 @ + 0x88 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM17 @ + 0x8c Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM18 @ + 0x90 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM19 @ + 0x94 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM20 @ + 0x98 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM21 @ + 0x9c Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM22 @ + 0xa0 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM23 @ + 0xa4 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM24 @ + 0xa8 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM25 @ + 0xac Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM26 @ + 0xb0 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM27 @ + 0xb4 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM28 @ + 0xb8 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM29 @ + 0xbc Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM30 @ + 0xc0 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.INSTR_MEM31 @ + 0xc4 Instruction memory mapping Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 val
Bits	Type	Reset	Name	Description
15:0	rw	0x0	val	Write-only access to instruction memory location N

flexDI.SM0_CLKDIV @ + 0xc8 Clock divider configuration Register Reset default = 0x10000, mask 0xffffff00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT_P 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRAC_P
Bits	Type	Reset	Name	Description
7:0				Reserved
15:8	rw	0x0	FRAC_P	Fractional part of clock divisor
31:16	rw	0x1	INT_P	Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

flexDI.SM0_EXECCTRL @ + 0xcc Execution and Behaviour Settings of state Machine Reset default = 0x1f000, mask 0xffffff9f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXEC_STALLED SIDE_EN SIDE_PINDIR JMP_PIN OUT_EN_SEL INLINE_OUT_EN OUT_STICKY WRAP_TOP... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...WRAP_TOP WRAP_BOTTOM   STATUS_SEL STATUS_N
Bits	Type	Reset	Name	Description
3:0	rw	0x0	STATUS_N	Comparison level for the MOV x, STATUS instruction
4	rw	0x0	STATUS_SEL	Comparison used for the MOV x, STATUS instruction. 0x0 → All-ones if TX FIFO level < N, otherwise all-zeroes 0x1 → All-ones if RX FIFO level < N, otherwise all-zeroes
6:5				Reserved
11:7	rw	0x0	WRAP_BOTTOM	After reaching wrap_top, execution is wrapped to this address.
16:12	rw	0x1f	WRAP_TOP	After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
17	rw	0x0	OUT_STICKY	Continuously assert the most recent OUT/SET to the pins
18	rw	0x0	INLINE_OUT_EN	If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < …)
23:19	rw	0x0	OUT_EN_SEL	Which data bit to use for inline OUT enable
28:24	rw	0x0	JMP_PIN	The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
29	rw	0x0	SIDE_PINDIR	If 1, side-set data is asserted to pin directions, instead of pin values
30	rw	0x0	SIDE_EN	If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible sideset width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
31	rw	0x0	EXEC_STALLED	If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

flexDI.SM0_SHIFTCTRL @ + 0xd0 Control Behaviour of the input/output shift registers for state machine N Reset default = 0xc0000, mask 0xffff0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FJOIN_RX FJOIN_TX PULL_THRESH PUSH_THRESH OUT_SHIFTDIR IN_SHIFTDIR AUTOPULL AUTOPUSH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits	Type	Reset	Name	Description
15:0				Reserved
16	rw	0x0	AUTOPUSH	Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
17	rw	0x0	AUTOPULL	Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
18	rw	0x1	IN_SHIFTDIR	1 = shift input shift register to right (data enters from left). 0 = to left.
19	rw	0x1	OUT_SHIFTDIR	1 = shift out of output shift register to right. 0 = to left.
24:20	rw	0x0	PUSH_THRESH	Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
29:25	rw	0x0	PULL_THRESH	Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
30	rw	0x0	FJOIN_TX	When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
31	rw	0x0	FJOIN_RX	When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.

flexDI.SM0_ADDR @ + 0xd4 Instruction Pointer Base Address of statemachine N Reset default = 0x0, mask 0x1f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SMPC BASE
Bits	Type	Reset	Name	Description
4:0	ro	0x0	SMPC BASE	Base Address of state Machine Instruction Pointer

flexDI.SM0_INSTR @ + 0xd8 Instruction Pointer of statemachine N Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMPC
Bits	Type	Reset	Name	Description
15:0	rw	0x0	SMPC	Read to see the instruction currently addressed by state machine N's program counter. Write to execute an instruction immediately (including jumps) and then resume execution.

flexDI.SM0_PINCTRL @ + 0xdc state machine pin control Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIDESET_COUNT SET_COUNT OUT_COUNT IN_BASE... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...IN_BASE SIDESET_BASE SET_BASE OUT_BASE
Bits	Type	Reset	Name	Description
4:0	rw	0x0	OUT_BASE	The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
9:5	rw	0x0	SET_BASE	The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
14:10	rw	0x0	SIDESET_BASE	The lowest-numbered pin that will be affected by a sideset operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
19:15	rw	0x0	IN_BASE	The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
25:20	rw	0x0	OUT_COUNT	The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
28:26	rw	0x0	SET_COUNT	The number of pins asserted by a SET. In the range 0 to 5 inclusive.
31:29	rw	0x0	SIDESET_COUNT	The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

flexDI.SM1_CLKDIV @ + 0xe0 Clock divider configuration Register Reset default = 0x10000, mask 0xffffff00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT_P 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRAC_P
Bits	Type	Reset	Name	Description
7:0				Reserved
15:8	rw	0x0	FRAC_P	Fractional part of clock divisor
31:16	rw	0x1	INT_P	Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

flexDI.SM1_EXECCTRL @ + 0xe4 Execution and Behaviour Settings of state Machine Reset default = 0x1f000, mask 0xffffff9f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXEC_STALLED SIDE_EN SIDE_PINDIR JMP_PIN OUT_EN_SEL INLINE_OUT_EN OUT_STICKY WRAP_TOP... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...WRAP_TOP WRAP_BOTTOM   STATUS_SEL STATUS_N
Bits	Type	Reset	Name	Description
3:0	rw	0x0	STATUS_N	Comparison level for the MOV x, STATUS instruction
4	rw	0x0	STATUS_SEL	Comparison used for the MOV x, STATUS instruction. 0x0 → All-ones if TX FIFO level < N, otherwise all-zeroes 0x1 → All-ones if RX FIFO level < N, otherwise all-zeroes
6:5				Reserved
11:7	rw	0x0	WRAP_BOTTOM	After reaching wrap_top, execution is wrapped to this address.
16:12	rw	0x1f	WRAP_TOP	After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
17	rw	0x0	OUT_STICKY	Continuously assert the most recent OUT/SET to the pins
18	rw	0x0	INLINE_OUT_EN	If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < …)
23:19	rw	0x0	OUT_EN_SEL	Which data bit to use for inline OUT enable
28:24	rw	0x0	JMP_PIN	The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
29	rw	0x0	SIDE_PINDIR	If 1, side-set data is asserted to pin directions, instead of pin values
30	rw	0x0	SIDE_EN	If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible sideset width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
31	rw	0x0	EXEC_STALLED	If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

flexDI.SM1_SHIFTCTRL @ + 0xe8 Control Behaviour of the input/output shift registers for state machine N Reset default = 0xc0000, mask 0xffff0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FJOIN_RX FJOIN_TX PULL_THRESH PUSH_THRESH OUT_SHIFTDIR IN_SHIFTDIR AUTOPULL AUTOPUSH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits	Type	Reset	Name	Description
15:0				Reserved
16	rw	0x0	AUTOPUSH	Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
17	rw	0x0	AUTOPULL	Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
18	rw	0x1	IN_SHIFTDIR	1 = shift input shift register to right (data enters from left). 0 = to left.
19	rw	0x1	OUT_SHIFTDIR	1 = shift out of output shift register to right. 0 = to left.
24:20	rw	0x0	PUSH_THRESH	Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
29:25	rw	0x0	PULL_THRESH	Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
30	rw	0x0	FJOIN_TX	When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
31	rw	0x0	FJOIN_RX	When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.

flexDI.SM1_ADDR @ + 0xec Instruction Pointer Base Address of statemachine N Reset default = 0x0, mask 0x1f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SMPC BASE
Bits	Type	Reset	Name	Description
4:0	ro	0x0	SMPC BASE	Base Address of state Machine Instruction Pointer

flexDI.SM1_INSTR @ + 0xf0 Instruction Pointer of statemachine N Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMPC
Bits	Type	Reset	Name	Description
15:0	rw	0x0	SMPC	Read to see the instruction currently addressed by state machine N's program counter. Write to execute an instruction immediately (including jumps) and then resume execution.

flexDI.SM1_PINCTRL @ + 0xf4 state machine pin control Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIDESET_COUNT SET_COUNT OUT_COUNT IN_BASE... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...IN_BASE SIDESET_BASE SET_BASE OUT_BASE
Bits	Type	Reset	Name	Description
4:0	rw	0x0	OUT_BASE	The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
9:5	rw	0x0	SET_BASE	The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
14:10	rw	0x0	SIDESET_BASE	The lowest-numbered pin that will be affected by a sideset operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
19:15	rw	0x0	IN_BASE	The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
25:20	rw	0x0	OUT_COUNT	The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
28:26	rw	0x0	SET_COUNT	The number of pins asserted by a SET. In the range 0 to 5 inclusive.
31:29	rw	0x0	SIDESET_COUNT	The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

flexDI.SM2_CLKDIV @ + 0xf8 Clock divider configuration Register Reset default = 0x10000, mask 0xffffff00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT_P 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRAC_P
Bits	Type	Reset	Name	Description
7:0				Reserved
15:8	rw	0x0	FRAC_P	Fractional part of clock divisor
31:16	rw	0x1	INT_P	Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

flexDI.SM2_EXECCTRL @ + 0xfc Execution and Behaviour Settings of state Machine Reset default = 0x1f000, mask 0xffffff9f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXEC_STALLED SIDE_EN SIDE_PINDIR JMP_PIN OUT_EN_SEL INLINE_OUT_EN OUT_STICKY WRAP_TOP... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...WRAP_TOP WRAP_BOTTOM   STATUS_SEL STATUS_N
Bits	Type	Reset	Name	Description
3:0	rw	0x0	STATUS_N	Comparison level for the MOV x, STATUS instruction
4	rw	0x0	STATUS_SEL	Comparison used for the MOV x, STATUS instruction. 0x0 → All-ones if TX FIFO level < N, otherwise all-zeroes 0x1 → All-ones if RX FIFO level < N, otherwise all-zeroes
6:5				Reserved
11:7	rw	0x0	WRAP_BOTTOM	After reaching wrap_top, execution is wrapped to this address.
16:12	rw	0x1f	WRAP_TOP	After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
17	rw	0x0	OUT_STICKY	Continuously assert the most recent OUT/SET to the pins
18	rw	0x0	INLINE_OUT_EN	If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < …)
23:19	rw	0x0	OUT_EN_SEL	Which data bit to use for inline OUT enable
28:24	rw	0x0	JMP_PIN	The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
29	rw	0x0	SIDE_PINDIR	If 1, side-set data is asserted to pin directions, instead of pin values
30	rw	0x0	SIDE_EN	If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible sideset width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
31	rw	0x0	EXEC_STALLED	If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

flexDI.SM2_SHIFTCTRL @ + 0x100 Control Behaviour of the input/output shift registers for state machine N Reset default = 0xc0000, mask 0xffff0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FJOIN_RX FJOIN_TX PULL_THRESH PUSH_THRESH OUT_SHIFTDIR IN_SHIFTDIR AUTOPULL AUTOPUSH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits	Type	Reset	Name	Description
15:0				Reserved
16	rw	0x0	AUTOPUSH	Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
17	rw	0x0	AUTOPULL	Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
18	rw	0x1	IN_SHIFTDIR	1 = shift input shift register to right (data enters from left). 0 = to left.
19	rw	0x1	OUT_SHIFTDIR	1 = shift out of output shift register to right. 0 = to left.
24:20	rw	0x0	PUSH_THRESH	Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
29:25	rw	0x0	PULL_THRESH	Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
30	rw	0x0	FJOIN_TX	When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
31	rw	0x0	FJOIN_RX	When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.

flexDI.SM2_ADDR @ + 0x104 Instruction Pointer Base Address of statemachine N Reset default = 0x0, mask 0x1f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SMPC BASE
Bits	Type	Reset	Name	Description
4:0	ro	0x0	SMPC BASE	Base Address of state Machine Instruction Pointer

flexDI.SM2_INSTR @ + 0x108 Instruction Pointer of statemachine N Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMPC
Bits	Type	Reset	Name	Description
15:0	rw	0x0	SMPC	Read to see the instruction currently addressed by state machine N's program counter. Write to execute an instruction immediately (including jumps) and then resume execution.

flexDI.SM2_PINCTRL @ + 0x10c state machine pin control Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIDESET_COUNT SET_COUNT OUT_COUNT IN_BASE... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...IN_BASE SIDESET_BASE SET_BASE OUT_BASE
Bits	Type	Reset	Name	Description
4:0	rw	0x0	OUT_BASE	The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
9:5	rw	0x0	SET_BASE	The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
14:10	rw	0x0	SIDESET_BASE	The lowest-numbered pin that will be affected by a sideset operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
19:15	rw	0x0	IN_BASE	The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
25:20	rw	0x0	OUT_COUNT	The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
28:26	rw	0x0	SET_COUNT	The number of pins asserted by a SET. In the range 0 to 5 inclusive.
31:29	rw	0x0	SIDESET_COUNT	The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

flexDI.SM3_CLKDIV @ + 0x110 Clock divider configuration Register Reset default = 0x10000, mask 0xffffff00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT_P 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRAC_P
Bits	Type	Reset	Name	Description
7:0				Reserved
15:8	rw	0x0	FRAC_P	Fractional part of clock divisor
31:16	rw	0x1	INT_P	Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

flexDI.SM3_EXECCTRL @ + 0x114 Execution and Behaviour Settings of state Machine Reset default = 0x1f000, mask 0xffffff9f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXEC_STALLED SIDE_EN SIDE_PINDIR JMP_PIN OUT_EN_SEL INLINE_OUT_EN OUT_STICKY WRAP_TOP... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...WRAP_TOP WRAP_BOTTOM   STATUS_SEL STATUS_N
Bits	Type	Reset	Name	Description
3:0	rw	0x0	STATUS_N	Comparison level for the MOV x, STATUS instruction
4	rw	0x0	STATUS_SEL	Comparison used for the MOV x, STATUS instruction. 0x0 → All-ones if TX FIFO level < N, otherwise all-zeroes 0x1 → All-ones if RX FIFO level < N, otherwise all-zeroes
6:5				Reserved
11:7	rw	0x0	WRAP_BOTTOM	After reaching wrap_top, execution is wrapped to this address.
16:12	rw	0x1f	WRAP_TOP	After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.
17	rw	0x0	OUT_STICKY	Continuously assert the most recent OUT/SET to the pins
18	rw	0x0	INLINE_OUT_EN	If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < …)
23:19	rw	0x0	OUT_EN_SEL	Which data bit to use for inline OUT enable
28:24	rw	0x0	JMP_PIN	The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
29	rw	0x0	SIDE_PINDIR	If 1, side-set data is asserted to pin directions, instead of pin values
30	rw	0x0	SIDE_EN	If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible sideset width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
31	rw	0x0	EXEC_STALLED	If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

flexDI.SM3_SHIFTCTRL @ + 0x118 Control Behaviour of the input/output shift registers for state machine N Reset default = 0xc0000, mask 0xffff0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FJOIN_RX FJOIN_TX PULL_THRESH PUSH_THRESH OUT_SHIFTDIR IN_SHIFTDIR AUTOPULL AUTOPUSH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits	Type	Reset	Name	Description
15:0				Reserved
16	rw	0x0	AUTOPUSH	Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
17	rw	0x0	AUTOPULL	Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
18	rw	0x1	IN_SHIFTDIR	1 = shift input shift register to right (data enters from left). 0 = to left.
19	rw	0x1	OUT_SHIFTDIR	1 = shift out of output shift register to right. 0 = to left.
24:20	rw	0x0	PUSH_THRESH	Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32.
29:25	rw	0x0	PULL_THRESH	Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32.
30	rw	0x0	FJOIN_TX	When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.
31	rw	0x0	FJOIN_RX	When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed.

flexDI.SM3_ADDR @ + 0x11c Instruction Pointer Base Address of statemachine N Reset default = 0x0, mask 0x1f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SMPC BASE
Bits	Type	Reset	Name	Description
4:0	ro	0x0	SMPC BASE	Base Address of state Machine Instruction Pointer

flexDI.SM3_INSTR @ + 0x120 Instruction Pointer of statemachine N Reset default = 0x0, mask 0xffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMPC
Bits	Type	Reset	Name	Description
15:0	rw	0x0	SMPC	Read to see the instruction currently addressed by state machine N's program counter. Write to execute an instruction immediately (including jumps) and then resume execution.

flexDI.SM3_PINCTRL @ + 0x124 state machine pin control Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIDESET_COUNT SET_COUNT OUT_COUNT IN_BASE... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...IN_BASE SIDESET_BASE SET_BASE OUT_BASE
Bits	Type	Reset	Name	Description
4:0	rw	0x0	OUT_BASE	The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
9:5	rw	0x0	SET_BASE	The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
14:10	rw	0x0	SIDESET_BASE	The lowest-numbered pin that will be affected by a sideset operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
19:15	rw	0x0	IN_BASE	The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
25:20	rw	0x0	OUT_COUNT	The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
28:26	rw	0x0	SET_COUNT	The number of pins asserted by a SET. In the range 0 to 5 inclusive.
31:29	rw	0x0	SIDESET_COUNT	The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

flexDI.INTR @ + 0x128 Raw Interrupts Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM3 SM2 SM1 SM0 SM3_TXNFULL SM2_TXNFULL SM1_TXNFULL SM0_TXNFULL SM3_RXNEMPTY SM2_RXNEMPTY SM1_RXNEMPTY SM0_RXNEMPTY
Bits	Type	Reset	Name	Description
0	ro	0x0	SM0_RXNEMPTY	Empty flag of receive FIFO of SM0.
1	ro	0x0	SM1_RXNEMPTY	Empty flag of receive FIFO of SM1.
2	ro	0x0	SM2_RXNEMPTY	Empty flag of receive FIFO of SM2.
3	ro	0x0	SM3_RXNEMPTY	Empty flag of receive FIFO of SM3.
4	ro	0x0	SM0_TXNFULL	Full flag of transmit FIFO of SM0.
5	ro	0x0	SM1_TXNFULL	Full flag of transmit FIFO of SM1.
6	ro	0x0	SM2_TXNFULL	Full flag of transmit FIFO of SM2.
7	ro	0x0	SM3_TXNFULL	Full flag of transmit FIFO of SM3.
8	ro	0x0	SM0	Interrupt status of SM0.
9	ro	0x0	SM1	Interrupt status of SM1.
10	ro	0x0	SM2	Interrupt status of SM2.
11	ro	0x0	SM3	Interrupt status of SM3.

flexDI.IRQ0_INTE @ + 0x12c Interrupt Enable for irq0 Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM3 SM2 SM1 SM0 SM3_TXNFULL SM2_TXNFULL SM1_TXNFULL SM0_TXNFULL SM3_RXNEMPTY SM2_RXNEMPTY SM1_RXNEMPTY SM0_RXNEMPTY
Bits	Type	Reset	Name	Description
0	rw	0x0	SM0_RXNEMPTY	Enable of receive FIFO empty interrupt of SM0.
1	rw	0x0	SM1_RXNEMPTY	Enable of receive FIFO empty interrupt of SM1.
2	rw	0x0	SM2_RXNEMPTY	Enable of receive FIFO empty interrupt of SM2.
3	rw	0x0	SM3_RXNEMPTY	Enable of receive FIFO empty interrupt of SM3.
4	rw	0x0	SM0_TXNFULL	Enable of transmit FIFO full interrupt of SM0.
5	rw	0x0	SM1_TXNFULL	Enable of transmit FIFO full interrupt of SM1.
6	rw	0x0	SM2_TXNFULL	Enable of transmit FIFO full interrupt of SM2.
7	rw	0x0	SM3_TXNFULL	Enable of transmit FIFO full interrupt of SM3.
8	rw	0x0	SM0	Interrupt enable of SM0.
9	rw	0x0	SM1	Interrupt enable of SM1.
10	rw	0x0	SM2	Interrupt enable of SM2.
11	rw	0x0	SM3	Interrupt enable of SM3.

flexDI.IRQ0_INTF @ + 0x130 Interrupt Force for irq0, needs to be cleared manually from here Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM3 SM2 SM1 SM0 SM3_TXNFULL SM2_TXNFULL SM1_TXNFULL SM0_TXNFULL SM3_RXNEMPTY SM2_RXNEMPTY SM1_RXNEMPTY SM0_RXNEMPTY
Bits	Type	Reset	Name	Description
0	rw	0x0	SM0_RXNEMPTY	Force receive FIFO empty interrupt of SM0.
1	rw	0x0	SM1_RXNEMPTY	Force receive FIFO empty interrupt of SM1.
2	rw	0x0	SM2_RXNEMPTY	Force receive FIFO empty interrupt of SM2.
3	rw	0x0	SM3_RXNEMPTY	Force receive FIFO empty interrupt of SM3.
4	rw	0x0	SM0_TXNFULL	Force transmit FIFO full interrupt of SM0.
5	rw	0x0	SM1_TXNFULL	Force transmit FIFO full interrupt of SM1.
6	rw	0x0	SM2_TXNFULL	Force transmit FIFO full interrupt of SM2.
7	rw	0x0	SM3_TXNFULL	Force transmit FIFO full interrupt of SM3.
8	rw	0x0	SM0	Force interrupt of SM0.
9	rw	0x0	SM1	Force interrupt of SM1.
10	rw	0x0	SM2	Force interrupt of SM2.
11	rw	0x0	SM3	Force interrupt of SM3.

flexDI.IRQ0_INTS @ + 0x134 Interrupt status after masking & forcing for irq0 Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM3 SM2 SM1 SM0 SM3_TXNFULL SM2_TXNFULL SM1_TXNFULL SM0_TXNFULL SM3_RXNEMPTY SM2_RXNEMPTY SM1_RXNEMPTY SM0_RXNEMPTY
Bits	Type	Reset	Name	Description
0	ro	0x0	SM0_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM0.
1	ro	0x0	SM1_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM1.
2	ro	0x0	SM2_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM2.
3	ro	0x0	SM3_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM3.
4	ro	0x0	SM0_TXNFULL	Masked interrupt of transmit FIFO full event of SM0.
5	ro	0x0	SM1_TXNFULL	Masked interrupt of transmit FIFO full event of SM1.
6	ro	0x0	SM2_TXNFULL	Masked interrupt of transmit FIFO full event of SM2.
7	ro	0x0	SM3_TXNFULL	Masked interrupt of transmit FIFO full event of SM3.
8	ro	0x0	SM0	Masked interrupt of SM0.
9	ro	0x0	SM1	Masked interrupt of SM1.
10	ro	0x0	SM2	Masked interrupt of SM2.
11	ro	0x0	SM3	Masked interrupt of SM3.

flexDI.IRQ1_INTE @ + 0x138 Interrupt Enable for irq1 Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM3 SM2 SM1 SM0 SM3_TXNFULL SM2_TXNFULL SM1_TXNFULL SM0_TXNFULL SM3_RXNEMPTY SM2_RXNEMPTY SM1_RXNEMPTY SM0_RXNEMPTY
Bits	Type	Reset	Name	Description
0	rw	0x0	SM0_RXNEMPTY	Enable of receive FIFO empty interrupt of SM0.
1	rw	0x0	SM1_RXNEMPTY	Enable of receive FIFO empty interrupt of SM1.
2	rw	0x0	SM2_RXNEMPTY	Enable of receive FIFO empty interrupt of SM2.
3	rw	0x0	SM3_RXNEMPTY	Enable of receive FIFO empty interrupt of SM3.
4	rw	0x0	SM0_TXNFULL	Enable of transmit FIFO full interrupt of SM0.
5	rw	0x0	SM1_TXNFULL	Enable of transmit FIFO full interrupt of SM1.
6	rw	0x0	SM2_TXNFULL	Enable of transmit FIFO full interrupt of SM2.
7	rw	0x0	SM3_TXNFULL	Enable of transmit FIFO full interrupt of SM3.
8	rw	0x0	SM0	Interrupt enable of SM0.
9	rw	0x0	SM1	Interrupt enable of SM1.
10	rw	0x0	SM2	Interrupt enable of SM2.
11	rw	0x0	SM3	Interrupt enable of SM3.

flexDI.IRQ1_INTF @ + 0x13c Interrupt Force for irq1, needs to be cleared manually from here Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM3 SM2 SM1 SM0 SM3_TXNFULL SM2_TXNFULL SM1_TXNFULL SM0_TXNFULL SM3_RXNEMPTY SM2_RXNEMPTY SM1_RXNEMPTY SM0_RXNEMPTY
Bits	Type	Reset	Name	Description
0	rw	0x0	SM0_RXNEMPTY	Force receive FIFO empty interrupt of SM0.
1	rw	0x0	SM1_RXNEMPTY	Force receive FIFO empty interrupt of SM1.
2	rw	0x0	SM2_RXNEMPTY	Force receive FIFO empty interrupt of SM2.
3	rw	0x0	SM3_RXNEMPTY	Force receive FIFO empty interrupt of SM3.
4	rw	0x0	SM0_TXNFULL	Force transmit FIFO full interrupt of SM0.
5	rw	0x0	SM1_TXNFULL	Force transmit FIFO full interrupt of SM1.
6	rw	0x0	SM2_TXNFULL	Force transmit FIFO full interrupt of SM2.
7	rw	0x0	SM3_TXNFULL	Force transmit FIFO full interrupt of SM3.
8	rw	0x0	SM0	Force interrupt of SM0.
9	rw	0x0	SM1	Force interrupt of SM1.
10	rw	0x0	SM2	Force interrupt of SM2.
11	rw	0x0	SM3	Force interrupt of SM3.

flexDI.IRQ1_INTS @ + 0x140 Interrupt status after masking & forcing for irq1 Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   SM3 SM2 SM1 SM0 SM3_TXNFULL SM2_TXNFULL SM1_TXNFULL SM0_TXNFULL SM3_RXNEMPTY SM2_RXNEMPTY SM1_RXNEMPTY SM0_RXNEMPTY
Bits	Type	Reset	Name	Description
0	ro	0x0	SM0_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM0.
1	ro	0x0	SM1_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM1.
2	ro	0x0	SM2_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM2.
3	ro	0x0	SM3_RXNEMPTY	Masked interrupt of receive FIFO empty event of SM3.
4	ro	0x0	SM0_TXNFULL	Masked interrupt of transmit FIFO full event of SM0.
5	ro	0x0	SM1_TXNFULL	Masked interrupt of transmit FIFO full event of SM1.
6	ro	0x0	SM2_TXNFULL	Masked interrupt of transmit FIFO full event of SM2.
7	ro	0x0	SM3_TXNFULL	Masked interrupt of transmit FIFO full event of SM3.
8	ro	0x0	SM0	Masked interrupt of SM0.
9	ro	0x0	SM1	Masked interrupt of SM1.
10	ro	0x0	SM2	Masked interrupt of SM2.
11	ro	0x0	SM3	Masked interrupt of SM3.

flexDI.FLEXDI_REV @ + 0x144 flexdi revision register Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 revision number... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...revision number
Bits	Type	Reset	Name	Description
31:0	ro	0x0	revision number	the revision number of the current flexdi design implementation

Verfication plan:

• Verilog testbench, self-testing

Verilog module: IRQ Adapter

Function:

• Manages internal State machine IRQs

• Manages external irq selection

Interface:

• IRQ line input from CPU

• configuration using DMA Adapter registers

Verfication plan:

• Verilog testbench, self-testing

Verilog module: IO Mapper

Function:

• GPIO selection Matrix

• allows for selection and/or driving of multiple GPIO ports by state machines

Interface:

• connection to GPIO Pins

Verfication plan:

• Verilog testbench, self-testing