Design Flow Reference

The following reference list of defined targets is automatically generated from the blocks instantiated in flow/__init__.py and defined in the flow/*.py files.

Please check Design Flow Recipes for how to use the design flow.

block libc

A small libc providing basic system functions such as printf, memcpy etc. (Baselibc)

target libc.build
Requires:

Builds library for static linking (.a).

block sw_monitor

Program for the RISC-V CPU

always_rebuild target sw_monitor.build
Requires:

Main program for simulation and later use on FPGA.

target sw_monitor.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_monitor.delta
Requires:

Differential image for fast loading in simulator

block sw_minimal

Program for the RISC-V CPU

always_rebuild target sw_minimal.build
Requires:

Main program for simulation and later use on FPGA.

target sw_minimal.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_minimal.delta
Requires:

Differential image for fast loading in simulator

block sw_test_sim_ddr

Program for the RISC-V CPU

always_rebuild target sw_test_sim_ddr.build
Requires:

Main program for simulation and later use on FPGA.

target sw_test_sim_ddr.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_test_sim_ddr.delta
Requires:

Differential image for fast loading in simulator

block sw_test_rvlab

Program for the RISC-V CPU

always_rebuild target sw_test_rvlab.build
Requires:

Main program for simulation and later use on FPGA.

target sw_test_rvlab.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_test_rvlab.delta
Requires:

Differential image for fast loading in simulator

block sw_test_irq

Program for the RISC-V CPU

always_rebuild target sw_test_irq.build
Requires:

Main program for simulation and later use on FPGA.

target sw_test_irq.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_test_irq.delta
Requires:

Differential image for fast loading in simulator

block sw_rlight

Program for the RISC-V CPU

always_rebuild target sw_rlight.build
Requires:

Main program for simulation and later use on FPGA.

target sw_rlight.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_rlight.delta
Requires:

Differential image for fast loading in simulator

block sw_dma

Program for the RISC-V CPU

always_rebuild target sw_dma.build
Requires:

Main program for simulation and later use on FPGA.

target sw_dma.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_dma.delta
Requires:

Differential image for fast loading in simulator

block sw_project

Program for the RISC-V CPU

always_rebuild target sw_project.build
Requires:

Main program for simulation and later use on FPGA.

target sw_project.run
Requires:

Reprogram bitstream via remote programmer control

always_rebuild target sw_project.delta
Requires:

Differential image for fast loading in simulator

block xbar

Crossbar switch generator using OpenTitan’s tlgen

target xbar.generate

Generate SystemVerilog sources

block reggen

Register generator using OpenTitan’s reggen

target reggen.generate

Generate SystemVerilog + C headers

block simlibs_questa

Xilinx simulation cell libraries for QuestaSim

target simlibs_questa.unisims

Library for functional simulation

target simlibs_questa.simprims

Library for timing-annotated netlist simulation

target simlibs_questa.secureip

Encrypted simulation model library

block srcs

Hardware sources

always_rebuild target srcs.srcs_noddr
Requires:

RTL + verification sources without DDR3

always_rebuild target srcs.srcs
Requires:

RTL + verification sources including DDR3

target srcs.lint
Requires:

Run static code quality assessment

block rvlab_mig

Xilinx DDR3 Memory Interface Generator (MIG) IP

target rvlab_mig.generate

Generate IP

block rvlab_fpga_top

Top-level FPGA design

target rvlab_fpga_top.rtl_elaborate
Requires:

RTL elaboration in Vivado

target rvlab_fpga_top.syn
Requires:

Synthesize FPGA netlist from RTL sources

target rvlab_fpga_top.pnr
Requires:

Place and route netlist

target rvlab_fpga_top.bitstream
Requires:

Generate bitstream from PNR result

target rvlab_fpga_top.program
Requires:

Load bitstream to FPGA

block student_rlight_tb

Module-level testbench

target student_rlight_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target student_rlight_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target student_rlight_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block student_tlul_mux_tb

Module-level testbench

target student_tlul_mux_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target student_tlul_mux_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target student_tlul_mux_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_instruction_decode_tb

Module-level testbench

target flexdi_instruction_decode_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_instruction_decode_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_instruction_decode_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_sm_gpio_mapper_tb

Module-level testbench

target flexdi_sm_gpio_mapper_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_sm_gpio_mapper_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_sm_gpio_mapper_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_sm_core_tb

Module-level testbench

target flexdi_sm_core_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_sm_core_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_sm_core_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_frac_clk_div_tb

Module-level testbench

target flexdi_frac_clk_div_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_frac_clk_div_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_frac_clk_div_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_gpio_prioritizer_tb

Module-level testbench

target flexdi_gpio_prioritizer_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_gpio_prioritizer_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_gpio_prioritizer_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_ff_synchronizer_tb

Module-level testbench

target flexdi_ff_synchronizer_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_ff_synchronizer_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_ff_synchronizer_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_inst_mem_tb

Module-level testbench

target flexdi_inst_mem_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_inst_mem_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_inst_mem_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_irq_ctrl_tb

Module-level testbench

target flexdi_irq_ctrl_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_irq_ctrl_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_irq_ctrl_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_fifo_module_tb

Module-level testbench

target flexdi_fifo_module_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_fifo_module_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_fifo_module_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block flexdi_fifo_tb

Module-level testbench

target flexdi_fifo_tb.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target flexdi_fifo_tb.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target flexdi_fifo_tb.sim_rtl_xsim
Requires:

RTL simulation with XSim

block systb_monitor

System testbench

target systb_monitor.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_monitor.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_monitor.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_monitor.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_monitor.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_monitor.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_monitor.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_monitor.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_monitor.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim

block systb_minimal

System testbench

target systb_minimal.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_minimal.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_minimal.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_minimal.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_minimal.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_minimal.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_minimal.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_minimal.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_minimal.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim

block systb_test_sim_ddr

System testbench

target systb_test_sim_ddr.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_test_sim_ddr.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_test_sim_ddr.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_test_sim_ddr.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_test_sim_ddr.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_test_sim_ddr.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_test_sim_ddr.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_test_sim_ddr.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_test_sim_ddr.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim

block systb_test_rvlab

System testbench

target systb_test_rvlab.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_test_rvlab.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_test_rvlab.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_test_rvlab.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_test_rvlab.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_test_rvlab.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_test_rvlab.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_test_rvlab.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_test_rvlab.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim

block systb_test_irq

System testbench

target systb_test_irq.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_test_irq.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_test_irq.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_test_irq.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_test_irq.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_test_irq.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_test_irq.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_test_irq.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_test_irq.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim

block systb_rlight

System testbench

target systb_rlight.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_rlight.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_rlight.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_rlight.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_rlight.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_rlight.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_rlight.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_rlight.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_rlight.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim

block systb_dma

System testbench

target systb_dma.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_dma.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_dma.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_dma.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_dma.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_dma.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_dma.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_dma.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_dma.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim

block systb_project

System testbench

target systb_project.sim_rtl_questa
Requires:

RTL simulation with QuestaSim

target systb_project.sim_rtl_questa_ddr
Requires:

RTL simulation with QuestaSim including DDR3

target systb_project.sim_rtl_questa_batch
Requires:

RTL simulation with QuestaSim (batch mode)

target systb_project.sim_synfunc_questa
Requires:

Post-synthesis functional simulation with QuestaSim

target systb_project.sim_pnrtime_questa
Requires:

Post-PNR timing simulation with QuestaSim

target systb_project.sim_rtl_xsim
Requires:

RTL simulation with XSim

target systb_project.sim_rtl_xsim_ddr
Requires:

RTL simulation with XSim including DDR3

target systb_project.sim_synfunc_xsim
Requires:

Post-synthesis functional simulation with XSim

target systb_project.sim_pnrtime_xsim
Requires:

Post-PNR timing simulation with XSim