Generated Registers

Register demo

regdemo.shiftout @ + 0x0 shifter output Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 val... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...val
Bits	Type	Reset	Name	Description
31:0	ro	0x0	val	value

regdemo.shiftin @ + 0x4 Shifter input Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 val... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...val
Bits	Type	Reset	Name	Description
31:0	rw	0x0	val	value

regdemo.shiftcfg @ + 0x8 Shifter config Reset default = 0x0, mask 0x3f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   amt dir
Bits	Type	Reset	Name	Description
0	rw	0x0	dir	direction: 0 = left, 1 = right
5:1	rw	0x0	amt	shift amount

DDR3 control

ddr_ctrl.temp @ + 0x0 ADC temperature Reset default = 0x0, mask 0xfff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   rdata
Bits	Type	Reset	Name	Description
11:0	ro	0x0	rdata	value

ddr_ctrl.status @ + 0x4 DDR MIG status Reset default = 0x0, mask 0x3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   calib_complete present
Bits	Type	Reset	Name	Description
0	ro	0x0	present	DDR / MIG present
1	ro	0x0	calib_complete	DDR initial calibration complete

ddr_ctrl.ctrl @ + 0x8 Control Reset default = 0x0, mask 0x1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   mig_rst_n
Bits	Type	Reset	Name	Description
0	rw	0x0	mig_rst_n	MIG reset (active low)

RISC-V timer

rv_timer.CTRL @ + 0x0 Control register Reset default = 0x0, mask 0x1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   active0
Bits	Type	Reset	Name	Description
0	rw	0x0	active0	If 1, timer operates for TIMER0

rv_timer.CFG0 @ + 0x100 Configuration for Hart 0 Reset default = 0x10000, mask 0xff0fff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   step 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   prescale
Bits	Type	Reset	Name	Description
11:0	rw	0x0	prescale	Prescaler to generate tick
15:12				Reserved
23:16	rw	0x1	step	Incremental value for each tick

rv_timer.TIMER_V_LOWER0 @ + 0x104 Timer value Lower Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 v... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...v
Bits	Type	Reset	Name	Description
31:0	rw	0x0	v	Timer value [31:0]

rv_timer.TIMER_V_UPPER0 @ + 0x108 Timer value Upper Reset default = 0x0, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 v... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...v
Bits	Type	Reset	Name	Description
31:0	rw	0x0	v	Timer value [63:32]

rv_timer.COMPARE_LOWER0_0 @ + 0x10c Timer value Lower Reset default = 0xffffffff, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 v... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...v
Bits	Type	Reset	Name	Description
31:0	rw	0xffffffff	v	Timer compare value [31:0]

rv_timer.COMPARE_UPPER0_0 @ + 0x110 Timer value Upper Reset default = 0xffffffff, mask 0xffffffff
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 v... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...v
Bits	Type	Reset	Name	Description
31:0	rw	0xffffffff	v	Timer compare value [63:32]

rv_timer.INTR_ENABLE0 @ + 0x114 Interrupt Enable Reset default = 0x0, mask 0x1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   IE0
Bits	Type	Reset	Name	Description
0	rw	0x0	IE0	Interrupt Enable for timer for TIMER0

rv_timer.INTR_STATE0 @ + 0x118 Interrupt Status Reset default = 0x0, mask 0x1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   IS0
Bits	Type	Reset	Name	Description
0	rw1c	0x0	IS0	Interrupt status for timer for TIMER0

rv_timer.INTR_TEST0 @ + 0x11c Interrupt test register Reset default = 0x0, mask 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   T0
Bits	Type	Reset	Name	Description
0	wo	x	T0	Interrupt test for timer for TIMER0